Content-type: text/html Man page of FJSVcpc

FJSVcpc

Section: Misc. Reference Manual Pages (3CPC)
Updated: 25 Aug 2004
Index Return to Main Contents
 

NAME

FJSVcpc - hardware performance counters for the Fujitsu SPARC64 family of processors  

 

DESCRIPTION

This man-page highlights the main differences in the implementation of the CPC package between UltraSPARC and SPARC64 microprocessors. Please refer to the cpc(3CPC) man-pages for the details on the cpc feature.

The FJSVcpc differs from the base Solaris 10 cpc package: The syntax for specifying cpu performance events is unified between the Fujitsu SPARC64 and UltraSPARC processors, but SPARC64-III has some dependencies with the event selection. The libraries and command binaries are located in standard directories other than the header files. The header files are located in a platform specific directory.

 

Event Specification Syntax for SPARC64 processors

The syntax for specifying events on SPARC64 family of processors is unified to UltraSPARC family of processors.

On SPARC64_III processors, the syntax for specifying the events is as follows:

 -c [ pic0=<event0> ][ ,pic1=<event1> ]
 [ ,pic2=<event2> ][ ,pic3=<event3> ]
 [ ,pic4=<event4> ][ ,pic5=<event5> ]
 [ ,sys ][ ,nouser ]

There are dependencies between pic0, pic1 and pic2 and also between pic3, pic4 and pic5. They were called as the pm0_view group and pm1_view group in the obsoleted interface on Solaris 8 and Solaris 9. Each events belong to the group number. Events should be specified to pic0, pic1 and pic2 from the same group number, and to pic3, pic4 and pic5 also. There is no dependency between the group of pic0, pic1 and pic2 and the another group of pic3, pic4 and pic5. Note: Any counters can be specified if it's considered dependencies.

By default only user events are counted; however, the sys keyword allows system (kernel) events to be counted as well. User event counting can be disabled by specifying the nouser keyword. The keywords pic counter may be omitted; they can be used to resolve ambiguities if they exist. The events can also be specified simply by the event name without the picN (N=0,1,2,3,4,5) prefix.

 

Examples of valid event specification for SPARC64_III

All of the following event specifications are valid on the SPARC64_III processors:

pic1=instr_utlb_miss

pic0=instr_commit,pic1=instr_utlb_miss,pic4=data_main_tlb_miss

instr_commit,instr_utlb_miss,data_main_tlb_miss

On SPARC64_V processors, the syntax for specifying the events is as follows:

The events that the cpc command should collect information about must be specified after the "-c" keyword in the command line as follows. Note: Any counters can be specified.

-c [ pic0=<event0> ][ ,pic1=<event1> ]
 [ ,pic2=<event2> ][ ,pic3=<event3> ]
 [ ,pic4=<event4> ][ ,pic5=<event5> ]
 [ ,pic6=<event6> ][ ,pic7=<event7> ]
 [ ,sys ][ ,nouser ]

The sys and nouser suffixes have the following meaning: by default (i.e. without specification sys , or nouser, or both of them) the cpc command will collect information about events that happened in user mode. Adding the sys suffix will force the cpc command collect information about events that happened in both user and system modes (if nouser is not used). Adding the nouser suffix will block collection of the events that happened in user mode. For example, adding only the nouser suffix will block collection of any event.

 

Location of CPC header files, libraries and commands

 

The FJSVcpc files are distributed acrooss /usr/platform/sun4us and /usr/platform/`uname -i` directories rather than under the usual /usr/ directory. Since a given Fujitsu system is most likely to have both CPC implimentation: the base Solaris cpc (SUNWcpc) files and the FJSVcpc files, user should specify the proper order in search paths by including location of FJSVcpc files before the standard directories.

Header Files

These are located under directory: /usr/platform/sun4us/include.


Note: CPC interfaces between SPARC64-III and SPARC64-V are not compatible. User should chose one for CPC specific application. For SPARC64-III CPU the FJCPU and for SPARC64-V the FJPS1 macro should be defined at compilation time. These two macros are mutualy exclusive and cannot be used at the same time.

Libcpc.so & libpctx.so Shared Libraries

Located under /usr/lib directory. There are common libraries for all processors.

cputrack(1) command

Located under /usr/bin directory. Both 32-bit and 64-bit versions are provided.

cpustat(1M) command

Located under /usr/sbin directory.

 

List of Performance Counters

 

 

SPARC64_III specific counters

 

The following list of events for pic registers is taken from Appendix Q of SPARC64-III User's Guide. A number at the first column is group number which each events belong. The specified events should be same group number between pic0, pic1 and pic2 also between pic3, pic4 and pic5. Please refer to it a for detailed description.

pic0=<event0>
0,1,2,3,4,5,6,7,8instr_commit

pic1=<event1>
0instr_issue
1instr_utlb_miss
2fetch_stall
3reserv_queue_stall
4chkpt_srl_trap_stack_resrc_stall
5branch_issue
6ilt_miss
7l1_instr_cache_reload
8sync_event

pic2=<event2>
0cycle_cnt
1instr_main_tlb_miss
2psu_kill_stall
3free_reg_resrc_stall
4other_stall
5branch_mispredict
6i0_instr_cache_miss
7l1_instr_cache_invalid
8sync_cycle

pic3=<event3>
0mem_total_latency
1l1_data_cache_reload_load_event
2l1_data_cache_retag_event
3data_utlb_miss
4u2_cache_miss_instr_fetch
5u2_cache_miss_wrback
6u2_cache_hit_read_to_own_upa_trans

pic4=<event4>
0l1_data_cache_hit
1l1_data_cache_reload_store_event
2l1_data_cache_victim_cpback_event
3data_main_tlb_miss
4u2_cache_miss_data_load
5u2_cache_invalid_upa_trans
6non_cacheable_load

pic5=<event5>
0mem_access_event
1l1_data_cache_invalid_event
2l1_data_cache_unsolicit_cpback_event
3upa_access
4u2_cache_miss_data_store
5u2_cache_unsolicit_cpback
6non_cacheable_store

 

 

SPARC64_V specific counters

 

The following sections contain descriptions of the events that might be specified. Note please, that the name in the parenthesis is the exact name that should be used in the command line to provide an event name for the picN and (N=0,1,2,3,4,5,6,7) parameters.

pic0. The following events can be specified for pic0:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_int_vector, sx_miss_wait_pf, sreq_cpi_count.

pic1. The following events can be specified for pic1:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_all, sx_miss_wait_dm, sreq_bi_count.

pic2. The following events can be specified for pic2:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_spill, write_op_uTLB, sx_miss_count_pf, sreq_cpd_count.

pic3. The following events can be specified for pic3:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_int_level, write_if_uTLB, sx_miss_count_dm, sreq_cpb_count.

pic4. The following events can be specified for pic4:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_trap_inst, op_r_iu_req_mi_go, sx_read_count_pf, upa_data_busy.

pic5. The following events can be specified for pic5:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_fill, if_r_iu_req_mi_go, sx_read_count_dm, upa_abus_busy.

pic6. The following events can be specified for pic6:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_DMMU_miss, op_wait_all, dvp_count_pf, asi_wr_bar.

pic7. The following events can be specified for pic7:

cycle_counts, instruction_counts, load_store_instructions, branch_instructions, floating_instructions, impdep2_instructions, prefetch_instructions, trap_IMMU_miss, if_wait_all, dvp_count_dm, asi_rd_bar.

 

SPARC64_V EVENTS

 

 

Instruction Statistics

Instruction statistics counters can be monitored by any SU or SL of any PICs. Performance Monitor Cycle Count (cycle_counts)

        Counter
any

Counts cycles when performance monitor is enabled. This is similar to %tick register, but can separate user vs system cycles, based on PCR.UT and PCR.ST selection.

Instruction Count (instruction_counts)

        Counter
any

This counter counts number of committed instructions For User or System mode counts, this counter is exact. Combined with cycle count (obtained from the %tick register or E1), provides instructions per cycle IPC = E2 / (Cycle Count) If E2 and E1 are both collected for User or System mode, IPC in User or System mode can be derived.

Load/Store Instruction Count (load_store_instructions)

        Counter
any

Note: committed load/store instruction count. Atomic load-store instructions are also counted.

Branch Instruction Count (branch_instructions)
                 Counter
any

Committed branch instruction count. CALL, JMPL and RETURN are also counted.

Floating Point Instruction Count (floating_instructions)

        Counter
any

Committed floating point operation (FPop1 and FPop2). Floating Multiple-and-Add instruction is not counted.

Impdep2 Instruction Count (impdep2_instructions)

        Counter
any

Committed Floating Multiply-and-Add instruction count.

Prefetch Instruction Count (prefetch_instructions)

        Counter
any

Committed prefetch instruction count.

 

Trap Related Statistics

All Traps Count (trap_all)

        Counter
pic1

Count all trap events. The value is equivalent to the sum of type-specific traps counters.

Interrupt Vector Trap Count (trap_int_vector)

        Counter
pic0

Count occurrence of interrupt_vector_trap.

Level Interrupt Trap Count (trap_int_level)

        Counter
pic3

Count occurrence of interrupt_level_n.

Spill Trap Count (trap_spill)

        Counter
pic2

Count occurrence of spill_n_normal, spill_n_other.

Fill Trap Count (trap_fill)

        Counter
pic5

Count occurrence of fill_n_normal, fill_n_other.

Software Instruction Trap (trap_trap_inst)

        Counter
pic4

Count occurrence of Tcc instructions.

Instruction MMU Miss Trap (trap_IMMU_miss)

        Counter
pic7

Count occurrence of fast_instruction_access_MMU_miss.

Data MMU Miss Trap (trap_DMMU_miss)

        Counter
pic6

Count occurrence of data_instruction_access_MMU_miss.

 

MMU Event Counters

Instruction uTLB Miss (write_if_uTLB)

        Counter
pic3

Count occurrence of instruction uTLB miss.

Data uTLB Miss (write_op_uTLB)

        Counter
pic2

Count occurrence of data uTLB miss. Note: Occurrence of main TLB miss is counted by trap_IMMU_miss/ trap_DMMU_miss.

 

Cache Event Counters

I1 Cache Miss Count (if_r_iu_req_mi_go)

        Counter
pic5

Count occurrence of I1 cache miss.

D1 Cache Miss Count (op_r_iu_req_mi_go)

        Counter
pic4

Count occurrence of D1 cache miss.

I1 Cache Miss Latency (if_wait_all)

        Counter
pic7

Count total latency of I1 cache misses.

D1 Cache Miss Latency (op_wait_all)

        Counter
pic6

Count total latency of D1 cache misses.

L2 Cache Miss Wait Cycle by Demand Access (sx_miss_wait_dm)

        Counter
pic1

Amount of cycles from occurrence of a L2 cache miss to data returned, caused by demand access.

L2 Cache Miss Wait Cycle by Prefetch (sx_miss_wait_pf)

        Counter
pic0

Amount of cycles from occurrence of a L2 cache miss to data returned, caused by both software prefetch and hardware prefetch access.

L2 Cache Miss Count by Demand Access (sx_miss_count_dm)

        Counter
pic3

Count occurrence of L2 cache miss by demand access.

L2 Cache Miss Count by Prefetch (sx_miss_count_pf)

        Counter
pic2

Count occurrence of L2 cache miss by both software prefetch and hardware prefetch access.

L2 Cache Reference by Demand Access (sx_read_count_dm)

        Counter
pic5

Count L2 cache reference by demand read access.

L2 Cache Reference by Prefetch (sx_read_count_pf)

        Counter
pic4

Count L2 cache reference by both software prefetch and hardware prefetch access.

DVP count by Demand Miss (dvp_count_dm)

        Counter
pic7

Count occurrence of L2 cache miss by demand, with writeback request.

DVP count by Prefetch Miss (dvp_count_pf)

        Counter
pic6

Count occurrence of L2 cache miss by both software prefetch and hardware prefetch, with writeback request

 

UPA Event Counter

UPA event counters count how many S_REQ_xxx requests a CPU receives in a given time.

INV receive count (sreq_bi_count)

        Counter
pic1

Count number of S_INV_REQ packets received.

CPI receive count (sreq_cpi_count)

        Counter
pic0

Count number of S_CPI_REQ packets received.

CPB receive count (sreq_cpb_count)

        Counter
pic3

Count number of S_CPB_REQ packets received.

CPD receive count (sreq_cpd_count)

        Counter
pic2

Count number of S_CPD_REQ packets received.

UPA Address Bus Busy Cycle (upa_abus_busy)

        Counter
pic5

Amount of bus busy cycle of UPA address bus. Unit of this counter is UPA bus clock, not CPU clock.

UPA Data Bus Busy Cycle (upa_data_busy)

        Counter
pic4

Amount of bus busy cycle of UPA data bus. Unit of this counter is UPA bus clock, not CPU clock.

 

Miscellaneous Counter

Barrier Assist ASI Read Count (asi_rd_bar)

        Counter
pic7

Amount of read access to the barrier assist ASI registers.

Barrier Assist ASI Write Count (asi_wr_bar)

        Counter
pic6

Amount of write access to the barrier assist ASI registers.

 

SEE ALSO

cpc(3CPC), cputrack(1), cpustat(1M), cpc_bind_curlwp(3CPC), cpc_buf_create(3CPC), cpc_enable(3CPC), cpc_npic(3CPC), cpc_open(3CPC), cpc_set_create(3CPC), cpc_seterrhndlr(3CPC), libcpc(3LIB), pctx_capture(3CPC), pctx_set_events(3CPC), proc(4).


 

Index

NAME
DESCRIPTION
Event Specification Syntax for SPARC64 processors
Examples of valid event specification for SPARC64_III
Location of CPC header files, libraries and commands
List of Performance Counters
SPARC64_III specific counters
SPARC64_V specific counters
SPARC64_V EVENTS
Instruction Statistics
Trap Related Statistics
MMU Event Counters
Cache Event Counters
UPA Event Counter
Miscellaneous Counter
SEE ALSO

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Time: 02:39:07 GMT, October 02, 2010