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vme_univ_manual_setup

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NAME

vme_univ_manual_setup, sys_attrs_vba_univ - Describes how to set up UNIVERSE-II-based Alpha VME systems for use on the VMEbus, including how to modify attributes of the vba_univ kernel subsystem  

DESCRIPTION

VME UNIVERSE II manual setup allows you to run the Compaq Tru64 UNIX software on UNIVERSE-II-based Alpha VME systems.

For information about setting up VIP/VIC-based Alpha VME systems for use on the VMEbus, see the vme_manual_setup(7) reference page.

This reference page addresses the following topics relating to the use of the VMEbus on UNIVERSE-II-based Alpha VME systems: Configuring the vba_univ subsystem Configuring PCI-to-VME address spaces Configuring a special A24/A16 PCI-to-VME window Configuring VME-to-PCI address spaces Mapping UNIVERSE II CSRs to the VMEbus Mapping a location monitor window to the VMEbus Configuring VMEbus interrupts Using VMEbus software byte swapping Sharing memory between big/little endian processors VMEbus slave block transfers VMEbus master block transfers with local DMA Realtime interrupt-handling function rt_post_callout  

Configuring the vba_univ Subsystem

This section describes how to configure the vba_univ kernel subsystem in order to prepare UNIVERSE-II-based Alpha VME systems for use on the VMEbus.

You configure the UNIVERSE II adapter by examining the default attributes that Compaq supplies for the vba_univ subsystem, determining which attributes (if any) you want to change, then modifying the /etc/sysconfigtab file on your machine. After modifying /etc/sysconfigtab, you must shut down the system and reboot.

Note

You should not directly edit /etc/sysconfigtab. Instead you should use the sysconfigdb facility, as described in the sysconfigdb(8) reference page. Compaq recommends that you maintain private sysconfigtab file fragments for vba_univ attributes and use sysconfigdb switches to add (-a -f), delete (-d), or merge (-m -f) vba_univ attribute values. The Examples section of vb(7) illustrates this approach. Additional guidelines for editing kernel subsystem attributes are provided in the sys_attrs(5) reference page. You must always reboot after changing vba_univ subsystem attributes.

You can modify values for the following UNIVERSE II adapter attributes; each list item corresponds to a section later in this reference page:

Adapter interrupt dispatch policy Adapter VME-to-PCI window maximum size Adapter DMA window maximum size PCI coupled window timer value PCI maximum retries PCI posted write transfer count PCI aligned burst size VMEbus request level VMEbus request mode VMEbus release mode VMEbus timeout period VMEbus arbitration mode VMEbus arbitration timeout period System controller VMEbus resets enable/disable VMEbus on and off counters for MBLTs

You can also configure VMEbus windows in the following ways; each list item corresponds to a section later in this reference page:

Configuring PCI-to-VME address spaces Configuring a special A24/A16 PCI-to-VME window Configuring VME-to-PCI address spaces Mapping UNIVERSE II CSRs to the VMEbus Mapping a location monitor window to the VMEbus

The defaults that Compaq supplies for various VMEbus parameters are listed below. The default values specified should provide proper VMEbus operation for most applications. Be careful when modifying these values; not all adapters support all fields. Parameter Default Meaning -------------------------------------------------------------------- VBA_ISR_Dispatch_Policy 1 Adapter interruupt dispatch
                                    policy is to process all
                                    interrupts for the current SPL
                                    level (only)

VBA_Max_PCI_Sg_Size 0x20000000 Maximum VME-to-PCI window size
                                    is 512 MB

VBA_Max_DMA_Wndw_Size 0x4000000 Maximum DMA window size is 64 MB

PCI_Coupled_Wndw_Tmr 0x2 Coupled Window Timer set to hold
                                    VMEbus for 32 PCI clock cycles
                                    after a coupled transaction

PCI_Max_Retry 0xF PCI maximum retries before
                                    signaling error set to 960
                                    (value*64)

PCI_Posted_Wrt_On_Cnt 0x0 PCI posted write transfer count
                                    is 128 bytes

PCI_Aligned_Burst_Size 0x1 PCI aligned burst size is 64
                                    bytes

VME_Br_Lev 0x3 Bus request level 3 for master
                                    cycles

VME_Fair_Req 0x1 VMEbus request mode is fair (not
                                    demand)

VME_Rel_Mode 0x1 Release mode is release on
                                    request (ROR)

VME_Bus_To 0x6 VMEbus timeout period is 512
                                    microseconds

VME_Arb_Mode 0x0 Arbitration mode is round robin

VME_Arb_To 0x1 VMEbus arbitration timeout
                                    period is 16 microseconds

VME_Syscon 0x1 Enable system controller VMEbus
                                    resets

VME_Von_D64 0x4 VMEbus On counter for D64 MBLT:
                                    hold bus tenure for 2048 bytes

VME_Voff_D64 0x9 VMEbus Off counter for D64 MBLT:
                                    DMA interleave is 4 microseconds

VME_Von_D32 0x2 VMEbus On counter for D32 MBLT:
                                    hold bus tenure for 512 bytes

VME_Voff_D32 0x9 VMEbus Off counter for D32 MBLT:
                                    DMA interleave is 4 microseconds -------------------------------------------------------------------- For the special A24/A16 PCI-to-VME (PCI slave) window: -------------------------------------------------------------------- VME_A24_A16_Wnd_Ena 1 Special A24/A16 PCI-to-VMEbus
                                    window (64 MB) is enabled

VME_A24_A16_Wnd_WP_Ena 1 Write posting enabled to the
                                    A24/A16 window

VME_A24_A16_Wnd_Dwdth 0xF A24/A16 window maximum data
                                    width is D32 (all quadrants)

PCI_SLSI_Base 0 Stores A24/A16 (64 MB) window
                                    base address (obtained from
                                    firmware)

VME_A24_Size 0xFF0000 Size of each A24 address space
                                    within the A24/A16 window is
                                    16MB-64KB

VME_A16_Size 0x10000 Size of each A16 address space
                                    within the A24/A16 window is
                                    64KB -------------------------------------------------------------------- For PCI-to-VMEbus (PCI slave) windows 0 through 7: -------------------------------------------------------------------- PCI_LSI_Base 0 Stores base address of the
                                    contiguous PCI dense space
                                    available for PCI-to-VME windows
                                    (obtained from firmware)

PCI_Mem_Avail 0 Stores number of bytes allocated by
                                    firmware for PCI-to-VME windows

PCI_Mem_Free 0 Stores number of bytes available
                                    for further PCI-to-VME window
                                    allocations

VME_Wnd0_Ena 1 Window 0 is enabled: VME_Wnd0_VME_Address 0x80000000 VME base address is 0x80000000 VME_Wnd0_Size 0x08000000 Size is 128 MB VME_Wnd0_AM_Space 2 A32 space VME_Wnd0_AM_Usr_Sprvsr 1 User mode VME_Wnd0_AM_Data_Prg 1 Data access VME_Wndn_Dwdth 2 Maximum data width is D32 VME_Wndn_WP_Ena 1 Write posting enabled VME_Wndn_Cycle_Sel 0 VMEbus single cycles only

VME_Wnd1_Ena 1 Window 1 is enabled: VME_Wnd1_VME_Address 0x80000000 VME base address is 0x80000000 VME_Wnd1_Size 0x08000000 Size is 128 MB VME_Wnd1_AM_Space 2 A32 space VME_Wnd1_AM_Usr_Sprvsr 1 User mode VME_Wnd1_AM_Data_Prg 2 Program access VME_Wndn_Dwdth 2 Maximum data width is D32 VME_Wndn_WP_Ena 1 Write posting enabled VME_Wndn_Cycle_Sel 0 VMEbus single cycles only

VME_Wnd2_Ena 1 Window 2 is enabled: VME_Wnd2_VME_Address 0x80000000 VME base address is 0x80000000 VME_Wnd2_Size 0x08000000 Size is 128 MB VME_Wnd2_AM_Space 2 A32 space VME_Wnd2_AM_Usr_Sprvsr 2 Supervisory mode VME_Wnd2_AM_Data_Prg 1 Data access VME_Wndn_Dwdth 2 Maximum data width is D32 VME_Wndn_WP_Ena 1 Write posting enabled VME_Wndn_Cycle_Sel 0 VMEbus single cycles only

VME_Wnd3_Ena 1 Window 3 is enabled: VME_Wnd3_VME_Address 0x80000000 VME base address is 0x80000000 VME_Wnd3_Size 0x08000000 Size is 128 MB VME_Wnd3_AM_Space 2 A32 space VME_Wnd3_AM_Usr_Sprvsr 2 Supervisory mode VME_Wnd3_AM_Data_Prg 2 Program access VME_Wndn_Dwdth 2 Maximum data width is D32 VME_Wndn_WP_Ena 1 Write posting enabled VME_Wndn_Cycle_Sel 0 VMEbus single cycles only

VME_Wnd4_Ena 1 Window 4 is enabled: VME_Wnd4_VME_Address 0x00FF0000 VME base address is 0xFF0000 VME_Wnd4_Size 0x00010000 Size is 64 KB VME_Wnd4_AM_Space 1 A24 space VME_Wnd4_AM_Usr_Sprvsr 1 User mode VME_Wnd4_AM_Data_Prg 1 Data access VME_Wndn_Dwdth 2 Maximum data width is D32 VME_Wndn_WP_Ena 1 Write posting enabled VME_Wndn_Cycle_Sel 0 VMEbus single cycles only

VME_Wnd5_Ena 1 Window 5 is enabled: VME_Wnd5_VME_Address 0x00FF0000 VME base address is 0xFF0000 VME_Wnd5_Size 0x00010000 Size is 64 KB VME_Wnd5_AM_Space 1 A24 space VME_Wnd5_AM_Usr_Sprvsr 2 Supervisory mode VME_Wnd5_AM_Data_Prg 1 Data access VME_Wndn_Dwdth 2 Maximum data width is D32 VME_Wndn_WP_Ena 1 Write posting enabled VME_Wndn_Cycle_Sel 0 VMEbus single cycles only

VME_Wnd6_Ena 0 Window 6 is disabled by default VME_Wnd6_VME_Address 0x0 VME_Wnd6_Size 0x0 VME_Wnd6_AM_Space 0 VME_Wnd6_AM_Usr_Sprvsr 1 VME_Wnd6_AM_Data_Prg 1 VME_Wndn_Dwdth 2 VME_Wndn_WP_Ena 1 VME_Wndn_Cycle_Sel 0

VME_Wnd7_Ena 0 Window 7 is disabled by default VME_Wnd7_VME_Address 0x0 VME_Wnd7_Size 0x0 VME_Wnd7_AM_Space 0 VME_Wnd7_AM_Usr_Sprvsr 1 VME_Wnd7_AM_Data_Prg 1 VME_Wndn_Dwdth 2 VME_Wndn_WP_Ena 1 VME_Wndn_Cycle_Sel 0 -------------------------------------------------------------------- For VMEbus-to-PCI (VME slave) windows 0 through 7: --------------------------------------------------------------------
                                    For all windows below (0-7): PCI_Wndn_AM_Usr_Sprvsr 3 Both user and supervisory mode PCI_Wndn_AM_Data_Prg 3 Both data and program access PCI_Wndn_WP_Ena 1 Write posting enabled PCI_Wndn_Pre_Rd_Ena 1 Prefetch reads enabled PCI_Wndn_PCI64_Ena 1 PCI64 transactions enabled PCI_Wndn_PCI_Lock_Ena 0 PCI bus lock disabled

PCI_Wnd0_Ena 1 Window 0 is enabled: PCI_Wnd0_VME_Address 0x00C00000 VME base address is 0xC00000 PCI_Wnd0_Size 0x00400000 Size is 4 MB PCI_Wnd0_AM_Space 1 A24 space

PCI_Wnd1_Ena 1 Window 1 is enabled: PCI_Wnd1_VME_Address 0x08000000 VME base address is 0x8000000 PCI_Wnd1_Size 0x08000000 Size is 128 MB PCI_Wnd1_AM_Space 2 A32 space

PCI_Wnd2_Ena 0 Window 2 is disabled by default PCI_Wnd2_VME_Address 0x0 PCI_Wnd2_Size 0x0 PCI_Wnd2_AM_Space 1

PCI_Wnd3_Ena 0 Window 3 is disabled by default PCI_Wnd3_VME_Address 0x0 PCI_Wnd3_Size 0x0 PCI_Wnd3_AM_Space 1

PCI_Wnd4_Ena 0 Window 4 is disabled by default PCI_Wnd4_VME_Address 0x0 PCI_Wnd4_Size 0x0 PCI_Wnd4_AM_Space 1

PCI_Wnd5_Ena 0 Window 5 is disabled by default PCI_Wnd5_VME_Address 0x0 PCI_Wnd5_Size 0x0 PCI_Wnd5_AM_Space 1

PCI_Wnd6_Ena 0 Window 6 is disabled by default PCI_Wnd6_VME_Address 0x0 PCI_Wnd6_Size 0x0 PCI_Wnd6_AM_Space 1

PCI_Wnd7_Ena 0 Window 7 is disabled by default PCI_Wnd7_VME_Address 0x0 PCI_Wnd7_Size 0x0 PCI_Wnd7_AM_Space 1 -------------------------------------------------------------------- For UNIVERSE II CSR and location monitor window mapping: -------------------------------------------------------------------- CSR_Ena 1 UNIVERSE II CSR mapping enabled: CSR_VME_Address 0xFFFF0000 VME base address is 0xFFFF0000 CSR_AM_Space 2 A32 space CSR_AM_Usr_Sprvsr 2 Supervisory mode CSR_AM_Data_Prg 3 Both program and data access

LM_Ena 0 Location monitor mapping is LM_VME_Address 0xFFFF1000 disabled by default LM_AM_Space 2 A32 space LM_AM_Usr_Sprvsr 2 Supervisory mode LM_AM_Data_Prg 3 Both program and data access The following VMEbus parameters pertain to VMEbus adapters that are not embedded SBC VMEbus designs. Embedded SBC VMEbus designs pass this information via another mechanism. Parameter Default Meaning -------------------------------------------------------------------- Irq0_SPL 4 VMEbus IRQ level to system SPL map Irq1_SPL 4 VMEbus IRQ 1 to SPL SPLDEVHIGH Irq2_SPL 4 VMEbus IRQ 2 to SPL SPLDEVHIGH Irq3_SPL 4 VMEbus IRQ 3 to SPL SPLDEVHIGH Irq4_SPL 4 VMEbus IRQ 4 to SPL SPLDEVHIGH Irq5_SPL 4 VMEbus IRQ 5 to SPL SPLDEVHIGH Irq6_SPL 4 VMEbus IRQ 6 to SPL SPLDEVHIGH Irq7_SPL 4 VMEbus IRQ 7 to SPL SPLDEVHIGH Adapt_Blk_SPL 4 Adapter resource blocking SPL
                            SPLDEVHIGH  

Specifying the Adapter Interrupt Dispatch Policy

You can specify one of the following values for the adapter interrupt dispatch policy (parameter VBA_ISR_Dispatch_Policy). Process all interrupts for the current SPL level (default) Process all interrupts for the current SPL level, then check for and process additional interrupts once  

Specifying the Adapter VME-to-PCI Window Maximum Size

You can specify a multiple of 64 KB (0x10000) up to 512 MB (0x20000000) for the adapter VME-to-PCI window maximum size (parameter VBA_Max_PCI_Sg_Size). 512 MB is the default.

The minimum window size of a VME-to-PCI window is is 64 KB. If the combined sizes of all enabled VME-to-PCI windows exceed the value of VBA_Max_PCI_Sg_Size, the adapter will not be configured. The parameter can be used to constrain consumption of PCI scatter/gather resources.  

Specifying the Adapter DMA Window Maximum Size

You can specify one of the following values for the adapter DMA window maximum size (parameter VBA_Max_DMA_Wndw_Size). 8 KB 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB 2 MB 4 MB 8 MB 16 MB 32 MB 64 MB (default) 128 MB 256 MB  

Specifying the PCI Coupled Window Timer Value

You can specify one of the following values for the PCI coupled window timer value (parameter PCI_Coupled_Wndw_Tmr). This value is stored in the PCI Miscellaneous Register (LMISC).

The Universe II adapter uses the coupled window timer to determine how long to hold ownership of the VMEbus on behalf of the PCI Slave Channel after processing a coupled transaction. The timer is restarted each time the Universe II processes a coupled transaction. If this timer expires, then the PCI Slave Channel releases the VME Master Interface. Disable Coupled Window Timer (CWT) CWT = 16 PCI clock cycles CWT = 32 PCI clock cycles (default) CWT = 64 PCI clock cycles CWT = 128 PCI clock cycles CWT = 256 PCI clock cycles CWT = 512 PCI clock cycles  

Specifying the PCI Maximum Retries

You can specify one of the following values for the number of PCI maximum retries before signaling errors (parameter PCI_Max_Retry). This value is stored in the Master Control Register (MAST_CTL). Retry forever (on PCI) Retry 64 times Retry 128 times Retry 192 times Retry 256 times Retry 320 times Retry 384 times Retry 448 times Retry 512 times Retry 576 times Retry 640 times Retry 704 times Retry 768 times Retry 832 times Retry 896 times Retry 960 times (default)  

Specifying the PCI Posted Write Transfer Count

You can specify one of the following values for the PCI posted write transfer count (parameter PCI_Posted_Wrt_On_Cnt). This value is stored in the Master Control Register (MAST_CTL). Posted write transfer count = 128 bytes (default) Posted write transfer count = 256 bytes Posted write transfer count = 512 bytes Posted write transfer count = 1024 bytes Posted write transfer count = 2048 bytes Posted write transfer count = 4096 bytes  

Specifying the PCI Aligned Burst Size

You can specify one of the following values for the PCI aligned burst size (parameter PCI_Aligned_Burst_Size). This value is stored in the Master Control Register (MAST_CTL). PCI aligned burst size = 32 bytes PCI aligned burst size = 64 bytes (default) PCI aligned burst size = 128 bytes  

Specifying the VMEbus Request Level

You can specify one of the following values for the VMEbus request level (parameter VME_Br_Lev). This value is stored in the Master Control Register (MAST_CTL). VMEbus request level BR0 VMEbus request level BR1 VMEbus request level BR2 VMEbus request level BR3 (default)  

Specifying the VMEbus Request Mode

You can specify one of the following values for the VMEbus request mode. This value is stored in the Master Control Register (MAST_CTL). Request mode is demand Request mode is fair (default)  

Specifying the VMEbus Release Mode

You can specify one of the following values for the release mode (parameter VME_Rel_Mode). This value is stored in the Master Control Register (MAST_CTL). Release when done, RWD Release on request, ROR (default)  

Specifying the VMEbus Timeout Period

You can specify one of the following values for the VMEbus timeout period (parameter VME_Bus_To). This value is stored in the Miscellaneous Control Register (MISC_CTL). Timeouts disabled Timeout = 16 microseconds Timeout = 32 microseconds Timeout = 64 microseconds Timeout = 128 microseconds Timeout = 256 microseconds Timeout = 512 microseconds (default)  

Specifying the VMEbus Arbitration Mode

You can specify one of the following values for the VMEbus arbitration mode (parameter VME_Arb_Mode). This value is stored in the Miscellaneous Control Register (MISC_CTL). This parameter is applicable only when the VMEbus adapter is configured to be the system controller. UNIVERSE II performs round-robin VMEbus arbitration (default) UNIVERSE II performs priority VMEbus arbitration  

Specifying the VMEbus Arbitration Timeout Period

You can specify one of the following values for the VMEbus arbitration timeout period (parameter VME_Arb_To). This value is stored in the Miscellaneous Control Register (MISC_CTL). Timeouts disabled Timeout = 16 microseconds (default) Timeout = 256 microseconds  

Specifying System Controller VMEbus Resets

You can specify one of the following values to indicate whether or not the adapter should issue VMEbus resets if it is the system controller (parameter VME_Syscon). This value is stored in the Miscellaneous Control Register (MISC_CTL).

For Alpha VME SBCs, in addition to specifying a value from this list, the configuration switches must be set accordingly to indicate whether or not the SBC is the VMEbus system controller. See the SBC's installation guide for information on setting the module configuration switches.

There must be one and only one system controller in the VMEbus backplane. The system controller must be electrically the first module in the VMEbus backplane and in most systems must be in the first VMEbus slot. Do not issue VMEbus resets if system controller Issue VMEbus resets if system controller (default)

The values specified interact with the VMEbus initialization code to determine whether a VMEbus reset is issued when the VMEbus adapter is being configured. If the value is set to 1 and the system being booted is the system controller, as determined by the VMEbus initialization code, a VMEbus reset is issued. If you do not want a VMEbus reset issued during VMEbus adapter configuration, set the value to zero (0). These values pertain only to the system controller.

If the system controller is configured to issue a VMEbus reset during adapter initialization, and other processor modules are installed in the VMEbus backplane, boot the system controller first to allow devices and processor modules to perform their bus reset actions.  

Special Considerations for VMEbus Resets

The system controller should always be the initiator of VMEbus resets. However, under certain error conditions, other VMEbus adapter modules may invoke a VMEbus reset. Modules installed in the VMEbus backplane react to bus resets differently. Some modules, if configured, perform a module reset. Some VMEbus adapters may have their VMEbus interface reset to a powerup state without notification to the operating system. This could leave the VMEbus adapter in an unconfigured state, cause unwanted effects to the operating system and its device drivers, and cause VMEbus errors to occur. Other VMEbus adapters on the VMEbus may accept VMEbus resets and attempt to reconfigure the VMEbus adapter to the hardware context it was running before the bus reset occurred. However, device drivers expecting interrupts may not receive them and I/O hardware operations may be canceled by the VMEbus reset without notification to the device driver. There is also a potential for data corruption to occur when the VMEbus adapter is reset during an I/O operation.

Compaq recommends that the system controller be the initiator of VMEbus resets during adapter initialization. If the system controller is not controlled by a processor, then a powerup sequence should cause all VMEbus adapters and devices to be reset. All modules on the VMEbus should perform a module reset upon detection of a bus reset. VMEbus adapters that are not the system controller and that are running an operating system should be shut down in an orderly fashion prior to the system controller being booted. These VMEbus adapters should be rebooted after the system controller has been booted, providing the system controller is to be utilized and controlled by a processor.

For UNIVERSE-II-based Alpha VME SBCs, Compaq recommends that nodes that are not the system controller have their module configuration switch 3 set to Closed (resets the SBC module on VMEbus reset signal). When the VMEbus is reset, and the module switch is set to accept a VMEbus reset, nonsystem controller modules take a boot action and are reset to a powered state.

If the SBC module configuration switch 3 is set to Open (does not reset the SBC module on VMEbus reset signal), the VMEbus adapter software will receive a VMEbus reset interrupt upon detection of a bus reset. The VMEbus reset signal initializes the VMEbus adapter to its powerup state. The VMEbus reset interrupt service interface displays the following message on the console terminal: vba0 reset_inter: VMEbus reset detected The interrupt service interface then initializes the VMEbus adapter to its defaults and enables any previously enabled interrupt enable bits.

Do not set the SBC module configuration switch 3 to Open without considering the following side effects of receiving a VMEbus reset: device drivers expecting interrupts may not receive them and I/O hardware operations may be canceled by the VMEbus reset without notification to the device drivers. There is potential risk of data corruption depending upon I/O activity at the time a bus reset occurred.  

Specifying the VMEbus On and Off Counters For MBLTs

You can specify one of the following values for the VMEbus On Counter for D64 MBLTs (parameter VME_Von_D64) or the VMEbus On Counter for D32 MBLTs (parameter VME_Von_D32). This value is placed in the DMA General Control and Status Register (DGCS). All bytes transferred until done 256 byte boundry 512 byte boundry (D32 MBLT default) 1024 byte boundry 2048 byte boundry (D64 MBLT default) 4096 byte boundry 8192 byte boundry 16384 byte boundry

You can specify one of the following values for the VMEbus Off Counter for D64 MBLTs (parameter VME_Voff_D64) or the VMEbus Off Counter for D32 MBLTs (parameter VME_Voff_D32). This value is placed in the DMA General Control and Status Register (DGCS). 0 microseconds between VME tenures 16 microseconds between VME tenures 32 microseconds between VME tenures 64 microseconds between VME tenures 128 microseconds between VME tenures 256 microseconds between VME tenures 512 microseconds between VME tenures 1024 microseconds between VME tenures 2 microseconds between VME tenures 4 microseconds between VME tenures (default) 8 microseconds between VME tenures  

Configuring PCI-to-VME Address Spaces

As part of configuring the vba_univ kernel subsystem, you can configure up to eight PCI-to-VME (PCI slave) windows, numbered 0 through 7, for your system. Additionally you can map a special 64 MB window for VMEbus A24 and A16 accesses.

By default, the following PCI-to-VME windows are provided on your system: VMEbus base address 0x80000000, 128 MB, A32 user data VMEbus base address 0x80000000, 128 MB, A32 user program VMEbus base address 0x80000000, 128 MB, A32 supervisory data VMEbus base address 0x80000000, 128 MB, A32 supervisory program VMEbus base address 0x00FF0000, 64 KB, A24 user data VMEbus base address 0x00FF0000, 64 KB, A24 supervisory data VMEbus base address 0x00000000, 0, A16 user data VMEbus base address 0x00000000, 0, A16 user data 64 MB (4 equal quadrants for user data, user program, supervisory data, supervisory program), top 64 KB per quadrant window is A16

Firmware allocates between 512 MB (minimum) and 960 MB (maximum) of contiguous PCI dense space for PCI-to-VME windows 0 through 7, and an additional, separate 64 MB for the special A24/A16 window. The default windows 0 through 3 consume 512 MB; the default windows 4 and 5 consume 128 KB. Windows 6 and 7 can be used to map to other VMEbus address spaces, module switches, semaphores, location monitors, and so on. Between the special 64 MB A24/A16 window and the eight other windows, all of A16 and A24 space is available for access. The CPU can access a 128 MB window of A32 space with the default configuration. You have the ability to increase or decrease the size of the windows, change the VMEbus addresses and modifiers, and specify additional VMEbus windows.

When configuring PCI-to-VME address spaces, you must ensure that all VMEbus devices to which the CPU will perform I/O are configured within one or more of the PCI-to-VME windows. If window sizes and VMEbus addresses are changed at a later point, you must ensure that the VMEbus devices remain within the PCI-to-VME windows.

During system initialization, if the special A24/A16 PCI-to-VME window is enabled (vba_univ parameter VME_A24_A16_Wnd_Ena equals 1), the UNIVERSE II adapter support code obtains (from firmware) the PCI address of the 64 MB window that will be used for VMEbus A24 and A16 accesses and configures the window to match your vba_univ attribute settings. For more information about this window, see the section Configuring a Special A24/A16 PCI-to-VME Window.

The UNIVERSE II adapter support code then obtains (from firmware) the PCI start and end addresses of the contiguous PCI dense space available for mapping PCI-to-VME windows 0 through 7. If enough PCI dense space is available, windows 0 through 7 are then configured to match your vba_univ attribute settings.

For hardware reasons, PCI-to-VME windows 0 and 4 must be configured on a 4 KB boundary and their sizes must be a multiple of 4 KB. The remaining six windows must be configured on a 64 KB boundary and their sizes must be a multiple of 64 KB. The sizes of all windows together must not exceed the limit provided in firmware.

Each PCI-to-VME window has the following configurable parameters, which you can modify in the form of vba_univ subsystem attributes:

Window n enabled/disabled VMEbus base address Window size VMEbus address modifiers VMEbus maximum data width Write posting enabled/disabled VMEbus cycle type

When mapping to the VMEbus to fulfill a request, UNIVERSE II support code searches PCI-to-VME windows 0 through 7 in numerically ascending order, comparing the VMEbus address attributes in the request to the configured attributes of each window. The first window that satisfies the request is used. If none of the windows 0 through 7 satisfies the request, the support code checks against the special A24/A16 PCI-to-VMEbus window.

Note that for A24 and A16 access, the support code's VMEbus mapping algorithm allows windows 0 through 7 to take precedence over the special A24/A16 window. If you want to guarantee that CSR accesses are mapped through the special A24/A16 window, you must manipulate your system's PCI-to-VME window attributes such that the CSR mappings fall through to the special window.  

Enabling or Disabling a PCI-to-VME Window

You can specify one of the following values to the VME_Wndn_Ena attribute for a PCI-to-VME window, 0 through 7, to enable or disable that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). Window n is disabled (default for windows 6 and 7) Window n is enabled (default for windows 0 through 5)  

Specifying a PCI-to-VME Window VMEbus Base Address

To establish the VMEbus base address for a PCI-to-VME window, 0 through 7, you specify a hexadecimal address value to the VME_Wndn_VME_Address attribute. The value can be in the range 0x0 to 0xFFFFFFFF, but must fall within the addressable range of the VMEbus address space (A32, A24, or A16) selected for that window.

Windows 0 and 4 must be configured on 4 KB boundaries; the remaining six windows must be configured on 64 KB boundaries.  

Specifying a PCI-to-VME Window Size

To establish the size for a PCI-to-VME window, 0 through 7, you specify a hexadecimal size value to the VME_Wndn_Size attribute. The value can be in the range 0x0 to 0xFFFFFFFF, but must fall within the addressable range of the VMEbus address space (A32, A24, or A16) selected for that window.

Windows 0 and 4 must be sized to a multiple of 4 KB; the remaining six windows must be sized to a multiple of 64 KB.  

Specifying PCI-to-VME Window VMEbus Address Modifiers

You can specify one of the following values to the VME_Wndn_AM_Space attribute for a PCI-to-VME window, 0 through 7, to select the VMEbus address space for that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). A16 address space A24 address space A32 address space

You can specify one of the following values to the VME_Wndn_AM_Usr_Sprvsr attribute for a PCI-to-VME window, 0 through 7, to select user or supervisory mode for that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). User mode Supervisory mode

You can specify one of the following values to the VME_Wndn_AM_Data_Prg attribute for a PCI-to-VME window, 0 through 7, to select data or program access for that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). Data access Program access  

Specifying a PCI-to-VME Window VMEbus Maximum Data Width

You can specify one of the following values to the VME_Wndn_AM_Dwdth attribute for a PCI-to-VME window, 0 through 7, to select the VMEbus maximum data width for that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). VMEbus maximum data width = 8 bits VMEbus maximum data width = 16 bits VMEbus maximum data width = 32 bits (default) VMEbus maximum data width = 64 bits  

Specifying PCI-to-VME Window Write Posting

You can specify one of the following values to the VME_Wndn_WP_Ena attribute for a PCI-to-VME window, 0 through 7, to enable or disable write posting for that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). Write posting is disabled Write posting is enabled (default)  

Specifying a PCI-to-VME Window VMEbus Cycle Type

You can specify one of the following values to the VME_Wndn_Cycle_Sel attribute for a PCI-to-VME window, 0 through 7, to select the VMEbus cycle type for that window. This value is placed in the PCI Slave Image Control Register corresponding to the PCI-to-VME window number (LSIn_CTL). Single cycles only (default) Single cycles and block transfers  

Configuring a Special A24/A16 PCI-to-VME Window

As part of configuring the vba_univ kernel subsystem, you can configure up to eight PCI-to-VME (PCI slave) windows for your system. Additionally, you can map a special A24/A16 PCI-to-VME window, 64 MB in size, for VMEbus A24 and A16 accesses.

The 64 MB window (64 MB aligned) is subdivided into four 16 MB windows. The top 64 KB of each 16 MB quadrant is used for VME A16 accesses. The remaining (16 MB minus 64 KB) of each quadrant is used for VME A24 accesses.

By default, the four quadrants of the 64 MB window are set up with the following VMEbus address-modifier attributes: User mode, data access User mode, program access Supervisory mode, data access Supervisory mode, program access

Window attributes apply to both A24 and A16 accesses within a quadrant. For example, for an A16 access to the top 64 KB of Window 2, the UNIVERSE II adapter would assert an A16 supervisory data address modifier. For an A24 access to the bottom 16MB-64KB of Window 2, the UNIVERSE II adapter would assert an A24 supervisory data address modifier.

The special A24/A16 PCI-to-VME window has the following configurable parameters, which you can modify in the form of vba_univ subsystem attributes:

Window enabled/disabled Write posting enbled/disabled VMEbus maximum data width

During system initialization, if the special A24/A16 PCI-to-VME window is enabled (vba_univ parameter VME_A24_A16_Wnd_Ena equals 1), the UNIVERSE II adapter interface obtains (from firmware) the PCI address of the 64 MB window that will be used for VMEbus A24 and A16 accesses and configures the window to match your vba_univ attribute settings.  

Enabling or Disabling the A24/A16 Window

You can specify one of the following values to the VME_A24_A16_Wnd_Ena attribute to enable or disable the special A24/A16 PCI-to-VMEbus window. This value is placed in the Special PCI Slave Image Register (SLSI). A24/A16 window is disabled A24/A16 window is enabled (default)  

Specifying A24/A16 Window Write Posting

You can specify one of the following values to the VME_A24_A16_Wnd_WP_Ena attribute to enable or disable write posting to the A24/A16 window. This value is placed in the Special PCI Slave Image Register (SLSI). Write posting is disabled Write posting is enabled (default)  

Specifying the A24/A16 Window VMEbus Maximum Data Width

You can specify one of the following values to the VME_A24_A16_Wnd_Dwdth attribute to select the A24/A16 window VMEbus maximum data width for each quadrant. This value is placed in the Special PCI Slave Image Register (SLSI). All quadrants maximum data width = 16 bits Quadrant 1 = 32 bits, others = 16 bits Quadrant 2 = 32 bits, others = 16 bits Quadrants 1 and 2 = 32 bits, others = 16 bits Quadrant 3 = 32 bits, others = 16 bits Quadrants 1 and 3 = 32 bits, others = 16 bits Quadrants 2 and 3 = 32 bits, others = 16 bits Quadrants 1, 2, and 3 = 32 bits, other = 16 bits Quadrant 4 = 32 bits, others = 16 bits Quadrants 1 and 4 = 32 bits, others = 16 bits Quadrants 2 and 4 = 32 bits, others = 16 bits Quadrants 1, 2, and 4 = 32 bits, other = 16 bits Quadrants 3 and 4 = 32 bits, others = 16 bits Quadrant 1, 3, and 4 = 32 bits, other = 16 bits Quadrant 2, 3, and 4 = 32 bits, other = 16 bits All quadrants maximum data width = 32 bits (default)  

Configuring VME-to-PCI Address Spaces

As part of configuring the vba_univ kernel subsystem, you can configure up to eight VME-to-PCI (VME slave) windows, numbered 0 through 7, for your system.

The default configuration of VME-to-PCI windows provides a basic two-window view into PCI space from the VMEbus, as follows: VMEbus base address 0x00C00000, 4 MB, A24 user/supervisory data/program VMEbus base address 0x08000000, 128 MB, A32 user/supervisory data/program VMEbus base address 0x00000000, 0, A24 user/supervisory data/program VMEbus base address 0x00000000, 0, A24 user/supervisory data/program VMEbus base address 0x00000000, 0, A24 user/supervisory data/program VMEbus base address 0x00000000, 0, A24 user/supervisory data/program VMEbus base address 0x00000000, 0, A24 user/supervisory data/program VMEbus base address 0x00000000, 0, A24 user/supervisory data/program

Other windows can be enabled, or enabled windows can be reconfigured to provide a different view into PCI space from the VMEbus. Windows 0 and 4 must be configured on an 8 KB boundary and must be a multiple of 8 KB in size, in order to line up with the PCI scatter/gather mapping register on Alpha based platforms. The remaining six windows must be configured on a 64 KB boundary and be a multiple of 64 KB in size. The sizes of all windows together must not exceed the total amount of resources available in the system for VME-to-PCI mapping. The number of VME-to-PCI windows enabled in the system, their sizes, and the amount of memory in the system determines the PCI resources needed. The maximum memory provided for VME-to-PCI mapping is 512 MB.

Each VME-to-PCI window has the following configurable parameters, which you can modify in the form of vba_univ subsystem attributes:

Window n enabled/disabled VMEbus base address Window size VMEbus address modifiers Write posting enabled/disabled Prefetch reads enabled/disabled 64-bit PCI bus transactions enabled/disabled
 

Enabling or Disabling a VME-to-PCI Window

You can specify one of the following values to the PCI_Wndn_Ena attribute for a VME-to-PCI window, 0 through 7, to enable or disable that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). Window n is disabled (default for windows 2 through 7) Window n is enabled (default for windows 0 and 1)  

Specifying a VME-to-PCI Window VMEbus Base Address

To establish the VMEbus base address for a VME-to-PCI window, 0 through 7, you specify a hexadecimal address value to the PCI_Wndn_VME_Address attribute. The value can be in the range 0x0 to 0xFFFFFFFF, but must fall within the addressable range of the VMEbus address space (A32, A24, or A16) selected for that window.

Windows 0 and 4 must be configured on 8 KB boundaries to line up with the PCI scatter/gather mapping register on Alpha based systems; the remaining six windows must be configured on 64 KB boundaries.  

Specifying a VME-to-PCI Window Size

To establish the size for a VME-to-PCI window, 0 through 7, you specify a hexadecimal size value to the PCI_Wndn_Size attribute. The value can be in the range 0x0 to 0xFFFFFFFF, but must fall within the addressable range of the VMEbus address space (A32, A24, or A16) selected for that window.

Windows 0 and 4 must be sized to a multiple of 8 KB; the remaining six windows must be sized to a multiple of 64 KB.  

Specifying VME-to-PCI Window VMEbus Address Modifiers

You can specify one of the following values to the PCI_Wndn_AM_Space attribute for a VME-to-PCI window, 0 through 7, to select the VMEbus address space for that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). A24 address space A32 address space

You can specify one of the following values to the PCI_Wndn_AM_Usr_Sprvsr attribute for a VME-to-PCI window, 0 through 7, to select user mode, supervisory mode, or both for that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). User mode Supervisory mode Both user and supervisory mode

You can specify one of the following values to the PCI_Wndn_AM_Data_Prg attribute for a VME-to-PCI window, 0 through 7, to select data access, program access, or both for that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). Data access Program access Both data and program access  

Specifying VME-to-PCI Window Write Posting

You can specify one of the following values to the PCI_Wndn_WP_Ena attribute for a VME-to-PCI window, 0 through 7, to enable or disable write posting for that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). Write posting is disabled Write posting is enabled (default)  

Specifying VME-to-PCI Window Prefetch Reads

You can specify one of the following values to the PCI_Wndn_Pre_Rd_Ena attribute for a VME-to-PCI window, 0 through 7, to enable or disable prefetch reads for that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). Prefetch reads are disabled Prefetch reads are enabled (default)  

Specifying VME-to-PCI Window 64-Bit PCI Bus Transactions

You can specify one of the following values to the PCI_Wndn_PCI64_Ena attribute for a VME-to-PCI window, 0 through 7, to enable or disable 64-bit PCI bus transactions for that window. This value is placed in the VMEbus Slave Image Control Register corresponding to the VME-to-PCI window number (VSIn_CTL). 64-bit PCI bus transactions are disabled 64-bit PCI bus transactions are enabled (default)

Note

In order for a window to be configured for PCI 64-bit transactions, in addition to setting the window's PCI_Wndn_PCI64_Ena attribute, the PCI Bus Size (LCLSIZE) bit must be set in the Miscellaneous Status Register (MISC_STA).  

Mapping UNIVERSE II CSRs to the VMEbus

As part of configuring the vba_univ kernel subsystem, you can map UNIVERSE II CSRs (control/status registers) to the VMEbus for your system. UNIVERSE II CSRs occupy a 4 KB window and can be enabled to support four module switches, eight semaphores, and location monitors.

The default configuration of the UNIVERSE II CSRs window on the VMEbus is as follows: VMEbus base address 0xFFFF0000, 4KB, A32 supervisory data/program

You determine where in VMEbus space the UNIVERSE II CSRs are configured by modifying the following vba_univ subsystem attributes:

CSR window enabled/disabled VMEbus base address (4 KB aligned) VMEbus address modifiers
 

Enabling or Disabling the CSR Window

You can specify one of the following values to the CSR_Ena attribute to enable or disable the CSR window. This value is placed in the VMEbus Register Access Control Register (VRAI_CTL). CSR window is disabled CSR window is enabled  

Specifying a CSR Window VMEbus Base Address

To establish the VMEbus base address for the CSR window, you specify a hexadecimal address value to the CSR_VME_Address attribute. The value can be in the range 0x0 to 0xFFFFFFFF, but must fall within the addressable range of the VMEbus address space (A32, A24, or A16) selected for that window. The CSR window must be configured on a 4 KB boundary.  

Specifying CSR Window VMEbus Address Modifiers

You can specify one of the following values to the CSR_AM_Space attribute to select the VMEbus address space for the CSR window. This value is placed in the VMEbus Register Access Control Register (VRAI_CTL). A16 address space A24 address space A32 address space

You can specify one of the following values to the CSR_AM_Usr_Sprvsr attribute to select user mode, supervisory mode, or both for the CSR window. This value is placed in the VMEbus Register Access Control Register (VRAI_CTL). User mode Supervisory mode Both user and supervisory mode

You can specify one of the following values to the CSR_AM_Data_Prg attribute to select data access, program access, or both for the CSR window. This value is placed in the VMEbus Register Access Control Register (VRAI_CTL). Data access Program access Both data and program access  

Mapping a Location Monitor Window to the VMEbus

As part of configuring the vba_univ kernel subsystem, you can map a 4 KB location monitor window to the VMEbus for your system. This window allows locations on the VMEbus to be monitored.

The default configuration of the location monitor window on the VMEbus is as follows: VMEbus base address 0xFFFF1000, 4KB, A32 supervisory data/program

This window can not reside within the VME-to-PCI windows you configure.

You determine where in VMEbus space the location monitor window is configured by modifying the following vba_univ subsystem attributes:

Location monitor window enabled/disabled VMEbus base address (4 KB aligned) VMEbus address modifiers

There is no specific operating system support for the location monitor registers and interrupts. Device drivers must install interrupt service interfaces and enable or disable location monitor interrupts. Any VMEbus read or write access to the UNIVERSE II location monitor window mapped to the VMEbus will then cause the appropriate location monitor interrupt to be generated. It is the device driver's responsibility to know the location monitor window's VMEbus base address and VMEbus address modifiers.  

Enabling or Disabling the Location Monitor Window

You can specify one of the following values to the LM_Ena attribute to enable or disable the location monitor window. This value is placed in the Location Monitor Control Register (LM_CTL). Location monitor window is disabled (default) Location monitor window is enabled  

Specifying a Location Monitor Window VMEbus Base Address

To establish the VMEbus base address for the location monitor window, you specify a hexadecimal address value to the LM_VME_Address attribute. The value can be in the range 0x0 to 0xFFFFFFFF, but must fall within the addressable range of the VMEbus address space (A32, A24, or A16) selected for that window. The location monitor window must be configured on a 4 KB boundary.  

Specifying Location Monitor Window VMEbus Address Modifiers

You can specify one of the following values to the LM_AM_Space attribute to select the VMEbus address space for the location monitor window. This value is placed in the Location Monitor Control Register (LM_CTL). A16 address space A24 address space A32 address space

You can specify one of the following values to the LM_AM_Usr_Sprvsr attribute to select user mode, supervisory mode, or both for the location monitor window. This value is placed in the Location Monitor Control Register (LM_CTL). User mode Supervisory mode Both user and supervisory mode

You can specify one of the following values to the LM_AM_Data_Prg attribute to select data access, program access, or both for the location monitor window. This value is placed in the Location Monitor Control Register (LM_CTL). Data access Program access Both data and program access  

Configuring VMEbus Interrupts

This section addresses VMEbus interrupt request levels.  

VMEbus Interrupt Request Levels

The system SPL levels at which VMEbus and VMEbus adapter interrupt requests are delivered to the operating system and device drivers are listed below: Interrupt Alpha VME SBC Request Name SPL Levels ------------------------------- VMEbus IRQ 1 SPLDEVLOW VMEbus IRQ 2 SPLDEVLOW VMEbus IRQ 3 SPLDEVLOW VMEbus IRQ 4 SPLDEVHIGH VMEbus IRQ 5 SPLDEVHIGH VMEbus IRQ 6 SPLDEVHIGH VMEbus IRQ 7 SPLDEVRT VMEbus Reset SPLDEVRT Module Switches SPLDEVRT VMEbus IACK SPLDEVLOW DMA Status SPLDEVRT Alpha VME SBCs do not support autovector requests.

As the previous list indicates, Alpha VME SBCs generate interrupt requests that higher-level interrupt requests can preempt.

On the Alpha VME SBCs, device drivers must use the rt_post_callout function for interrupts delivered at SPLDEVRT. Interrupt requests for which this is needed are VMEbus IRQ7 and any of the four module switch interrupts.  

Setting VMEbus Interrupt Vector Parameters

Refer to the Autoconfiguration Support section of Writing VMEbus Device Drivers for an example of adding and enabling VMEbus interrupts. Refer to the vme_handler_info structure in Writing VMEbus Device Drivers for interrupt handler information.

You specify vectors and interrupt requests (IRQs) for a device driver using the Vector and Bus_Priority fields of a VBA_Option entry in the /etc/sysconfigtab file or in a sysconfigtab file fragment.

Device drivers are passed this information in the controller structure elements ivnum and bus_priority.

VMEbus interrupt vectors 24 to 255 are available to device drivers. Vectors 0 to 23 are reserved by the VMEbus adapter. When you specify a vector to the Vector field of VBA_Option, you must also use the Bus_Priority field to specify an IRQ. Valid IRQ specifications are values 1 through 7. These values correspond to VMEbus levels IRQ1 through IRQ7.  

Specifying Module Switch Interrupt Vectors

Specify one of the following vectors in the Vector field of VBA_Option to select the module switch interrupt you want. Use the Bus_Priority field to specify 7 as the IRQ level. Vector 0x1140 Vector 0x1150 (default) Vector 0x1160 Vector 0x1170

Module switch interrupt vectors allow a module to issue an interrupt to itself or to another module. The autoconfiguration software provides control status registers (CSRs) for use in module switch interrupts. You can specify two CSRs in a VBA_Option entry in the /etc/sysconfigtab file or in a sysconfigtab file fragment. At boot time, the system searches for the specified CSRs.

The autoconfiguration software performs the appropriate bus mapping and provides io_handle_t values in the addr and addr2 members of the driver's controller structure. The addr argument is passed to the driver's probe interface, while the addr2 value must be obtained from the addr2 member of the controller structure.

For example, the following VBA_Option entry specifies an A16 window address as the CSR base address. The module switch 0 CSR is an offset from this A16 address. VBA_Option = Csr1 - 0x100, ..., Vector - 0x1140, Bus_Priority - 7, ... The driver structure allows you to specify the size, address type, and swap mode for the CSRs. For example, the following members in a driver structure indicate that the first CSR has a size of 256 bytes and is in the A16 address space: int addr1_size 256 int addr1_atype VME_A16_SUPER_ACC For more information, see Writing Device Drivers: Tutorial and Writing VMEbus Device Drivers, especially the sections on the addr and addr2 members of the controller structure and on the addr1_size, addr1_atype, addr2_size, and addr2_atype members of the driver structure.

In addition, you can use the vba_map_csr function to provide module switch interrupts. After using the vba_map_csr function to create an I/O handle, you write to an address derived from the base address plus an offset. Two write operations are performed, one signifying a clear and one a set. The following code fragment shows how the I/O handle is created: io_handle_t ioh; /* define type of ioh */ vme_addr_t A16base=0x100; /* base CSR address */ ioh = vba_map_csr(ctlr, A16base, 256,
                 (VME_A16_SUPER_ACC)); The following code fragment shows how the module switch interrupts are issued: write_io_port(ioh+0x34C, 1, 0, 0) /* write to CSR base address
                                      plus the offset to cause
                                      mailbox interrupt */ mb();  

Using VMEbus Software Byte Swapping

Alpha processors are little endian, while VMEbus is big endian. The default operation of the UNIVERSE II adapter causes the transfer of bytes between Alpha processors and VMEbus to be arranged correctly. If, however, a 16-bit or 32-bit number is needed in a VMEbus register, the default operation rearranges the bytes within the transfer such that the bytes are reversed in significance.

For UNIVERSE-II-based Alpha VME systems, software byte swapping must be used to handle these situations. (By contrast, VIP/VIC-based Alpha VME systems use hardware byte-swapping modes.)

For VMEbus device drivers, Compaq's Tru64 UNIX Device Driver Kit (DDK) provides a VMEbus example device driver, DMAEX, and accompanying user code that offers a model for how software byte swapping can be implemented. You can obtain VMEbus driver writing documentation by purchasing a DDK or by visiting Compaq's Tru64 UNIX or OEM web sites.

If your VMEbus device driver code must be portable across both VIP/VIC-based and UNIVERSE-II-based Alpha VME systems, you can code the driver to use hardware or software byte swapping according to the system type.  

Sharing Memory Between Big/Little Endian Processors

In a shared memory environment, where packed data structures in common memory are shared between an Alpha processor (little endian) and a big endian processor, software byte swapping is required to arrange bytes properly for 16- or 32-bit quantities (such as 16-bit counter values or 32-bit VMEbus address values).

Compaq recommends the following combination: UNIVERSE II default operation with software byte swapping on nonbyte data for the Alpha processor; and no swapping on the big endian processor.

Software swapping could be implemented with read/write macros that perform the swap with the following code. The purpose here is to provide code that would run on both little endian and big endian machines that have shared memory.
 #define read_word/long(iohandle,data)                     /
         data = read_io_port(iohandle,sizeof(word/long),0);/
 #ifdef LITTLEENDIAN                                       /
         swap_xx(data);                                    /
 #else /* BIGENDIAN */                                     /
 #endif
 #define write_word/long(iohandle,data)                    /
 #ifdef LITTLEENDIAN                                       /
         swap_xx(data);                                    /
 #else /* BIGENDIAN */                                     /
         write_io_port(iohandle,sizeof(word/long),0,data); /
 #endif  

VMEbus Slave Block Transfers

Alpha VME platforms are configured to accept slave block transfers (SBLTs) with data widths of D08, D16, D32, or D64 during adapter initialization. Once the SBC has mapped its memory onto the VMEbus by using the dma_map_alloc and dma_map_load functions, no other user interaction is needed.

Memory must be mapped to the VMEbus prior to D64 slave access.

Access to memory must coincide with the appropriate access mode. If you specify supervisory mode access when memory is mapped, memory accesses must use supervisory mode. If you specify user mode access, both supervisory and user access are allowed.  

VMEbus Master Block Transfers with Local DMA

The VMEbus interfaces for Alpha VME platforms provide a block-mode DMA engine. This DMA engine is capable of transferring up to (16 MB minus 2 KB) of data without processor intervention in VMEbus data widths of D08, D16, D32, or D64.

The DMA engine transfers data from the VMEbus to system memory (read) or from system memory to the VMEbus (write). The hardware interface handles the segmentation of the transfer. This ensures that the VMEbus specification is not violated in relation to crossing VMEbus 256-byte boundaries for D16 and D32 or 2-KB boundaries for D64.

The DMA engine is configured to give up the VMEbus during the transfer and to rearbitrate for the VMEbus again to continue the DMA. The time between when the DMA engine gives up the bus and rearbitrates for the bus is called the interleave period. During the interleave period, single-cycle VMEbus cycles, receipt of slave block transfers (SBLTs), or other operations may be performed.

The master block transfer (MBLT) hardware interface presents address modifiers of user block or supervisory block to the VMEbus, based on parameters passed in the Tru64 UNIX programming interface. The device or system on the VMEbus must be able to interpret these address modifiers; otherwise, bus errors may occur.

You can use the MBLT hardware interface to: Transfer data to and from those VMEbus devices that do not have their own DMA engine Move data between VMEbus device memory and system memory Transfer data to and from other systems that have their memory mapped to the VMEbus

The MBLT hardware interface supports DMA block-mode transfers to and from VMEbus A24 and A32 address space only.  

Interfaces for Master Block-Mode Transfers

To use the master block transfer (MBLT) with the local hardware DMA engine, you must invoke the following interfaces with specific flag values specified:
vba_set_dma_addr dma_map_alloc dma_map_load vba_dma dma_map_unload dma_map_dealloc

The vba_dma interface is used to start up and monitor the DMA engine. See the vba_dma() reference page for information on the vba_dma calling interface.

The flag values DMA_IN and DMA_OUT have specific meaning for VMEbus support with respect to the dma_map_alloc, dma_map_load, and vba_dma interfaces. These flags indicate to the low-level VMEbus dma_map_alloc, dma_map_load, and vba_dma interfaces that the MBLT hardware DMA engine is to be used and the direction of the transfer.

Specifying DMA_IN implies a read from the VMEbus to system memory. Specifying DMA_OUT implies a write from system memory to the VMEbus. You use the vba_set_dma_addr interface to pass the flag values and the VMEbus address at which the transfer is to occur.

The VMEbus block-mode DMA engine on the VMEbus adapter is a single entity that must be shared among various device drivers. Specifying DMA_SLEEP causes the device driver to block in the vba_dma interface if the DMA engine is already being utilized. If DMA_SLEEP is not specified and the DMA engine is being utilized, vba_dma returns an error indication.

The following sample code shows how to invoke the MBLT hardware DMA engine for a block-mode read operation. The code uses a VMEbus transfer width of D32 to invoke a 256 KB transfer from VMEbus address A24 0x400000 to system memory. The code also allocates resources to handle transfers up to 1 MB in size. This allows dma_map_load and vba_dma to be invoked multiple times with varying size buffers. You can change the code to perform writes by substituting DMA_OUT for DMA_IN.
  struct controller *ctlr;
  vme_addr_t        vme_addr = 0x40000;
  unsigned long     max_bc = (1024*1024);
  unsigned long     rtn_bc;
  char              *buffer;
  unsigned long     buffer_bc = (1024 * 256);
  sglist_t          dma_handle = (sglist_t)NULL;
  vme_atype_t       flags = (VME_A24_UDATA_D32|DMA_IN|DMA_SLEEP);
  int               rtn_flags;
  /*
   *  Allocate a buffer (256 KB) to be used for the transfer
   */
  MALLOC(buffer,(char *),buffer_bc,M_DEVBUF,M_WAITOK);
  /*
   *  Specify a VMEbus address of 0x40000
   *  Specify flags
   *     A24 address space
   *     User mode
   *     Select DMA engine for a read (DMA_IN) and
   *       wait for DMA engine (DMA_SLEEP)
   */
  rtn_flags = (int)vba_set_dma_addr(ctlr,flags,vme_addr);
  /*
   *  Allocate DMA resources for up to 1 Mbyte transfer
   *    Specify flags returned from vba_set_dma_addr() above.
   *    The return value from dma_map_alloc() should equal max_bc
   */
  rtn_bc = dma_map_alloc(max_bc,ctlr,&dma_handle,rtn_flags);
  /*
   *  Call dma_map_load() to load the resources for the
   *  DMA block-mode engine
   *    Specify the dma_handle returned from dma_map_alloc()
   *    Specify flags returned from vba_set_dma_addr().
   *    The return value from dma_map_load() should equal buffer_bc
   */
  rtn_bc = dma_map_load(buffer_bc,
                        (vm_offset_t)buffer,
                        0,
                        ctlr,
                        &dma_handle,
                        0,
                        rtn_flags);
  /*
   * Call vba_dma() to start up and monitor the VME adapter's block-mode
   *   DMA engine. Specify the dma_handle returned from dma_map_alloc.
   *   The return value from vba_dma() is the actual bytes transferred.
   *   This value should be the same as value buffer_bc. If not, then
   *   an error was detected during the transfer.
   */
  rtn_bc = vba_dma(ctlr,dma_handle);
  /*
   *  Unload and free DMA resources
   */
  dma_map_unload(0,dma_handle)
  dma_map_dealloc(dma_handle)  

Restriction on VMEbus Master Block Transfers

The following restriction applies to using master block transfers (MBLTs) on UNIVERSE-II-based Alpha VME platforms:

The data buffer address and the VME bus transfer address must be aligned exactly; that is, the lowest 2 bits must match.  

Realtime Interrupt-Handling Function rt_post_callout

Interrupt service interfaces (ISIs) executing at SPLDEVRT (SPL 6) must not call kernel interfaces directly. The rt_post_callout function allows the calling process to defer execution of a function until a time when kernel interfaces can be invoked. The function invoked by rt_post_callout runs at an elevated SPL and is subject to the same restrictions as an ISI.

The syntax for the rt_post_callout function is as follows:
   int (*function)(),
   long arg1,
   long arg2 ); The parameters for the rt_post_callout function are as follows: Name of the function to be invoked The first argument passed to the function The second argument passed to the function

If rt_post_callout is called again with the same function and arguments specified, then the duplicate invocation is dismissed before the first invocation has executed.

The following example is for an interrupt service interface (ISI) that runs at SPLDEVRT: rt_dev_intr(unit)
        int unit; {
 register struct rt_softc *sc = rt_softc[unit];
 rt_post_callout(user_wakeup_interface,   /* user wakeup function */
                 (long) &sc->error_recovery_flag, /* event to wake*/
                 (long) NULL);            /* unused argument      */
 return; } The following example shows a user-written function to wake up an event called by the rt_post_callout function: void user_wakeup_interface ( arg1, arg2 ) long arg1; long arg2; {
   thread_wakeup( (vm_offset_t) arg1); }  

RELATED INFORMATION

Interfaces: vb(7), vme_manual_setup(7), sysconfigdb(8), sys_attrs(5)

Writing VMEbus Device Drivers in the DIGITAL UNIX Device Driver Kit delim off


 

Index

NAME
DESCRIPTION
Configuring the vba_univ Subsystem
Specifying the Adapter Interrupt Dispatch Policy
Specifying the Adapter VME-to-PCI Window Maximum Size
Specifying the Adapter DMA Window Maximum Size
Specifying the PCI Coupled Window Timer Value
Specifying the PCI Maximum Retries
Specifying the PCI Posted Write Transfer Count
Specifying the PCI Aligned Burst Size
Specifying the VMEbus Request Level
Specifying the VMEbus Request Mode
Specifying the VMEbus Release Mode
Specifying the VMEbus Timeout Period
Specifying the VMEbus Arbitration Mode
Specifying the VMEbus Arbitration Timeout Period
Specifying System Controller VMEbus Resets
Special Considerations for VMEbus Resets
Specifying the VMEbus On and Off Counters For MBLTs
Configuring PCI-to-VME Address Spaces
Enabling or Disabling a PCI-to-VME Window
Specifying a PCI-to-VME Window VMEbus Base Address
Specifying a PCI-to-VME Window Size
Specifying PCI-to-VME Window VMEbus Address Modifiers
Specifying a PCI-to-VME Window VMEbus Maximum Data Width
Specifying PCI-to-VME Window Write Posting
Specifying a PCI-to-VME Window VMEbus Cycle Type
Configuring a Special A24/A16 PCI-to-VME Window
Enabling or Disabling the A24/A16 Window
Specifying A24/A16 Window Write Posting
Specifying the A24/A16 Window VMEbus Maximum Data Width
Configuring VME-to-PCI Address Spaces
Enabling or Disabling a VME-to-PCI Window
Specifying a VME-to-PCI Window VMEbus Base Address
Specifying a VME-to-PCI Window Size
Specifying VME-to-PCI Window VMEbus Address Modifiers
Specifying VME-to-PCI Window Write Posting
Specifying VME-to-PCI Window Prefetch Reads
Specifying VME-to-PCI Window 64-Bit PCI Bus Transactions
Mapping UNIVERSE II CSRs to the VMEbus
Enabling or Disabling the CSR Window
Specifying a CSR Window VMEbus Base Address
Specifying CSR Window VMEbus Address Modifiers
Mapping a Location Monitor Window to the VMEbus
Enabling or Disabling the Location Monitor Window
Specifying a Location Monitor Window VMEbus Base Address
Specifying Location Monitor Window VMEbus Address Modifiers
Configuring VMEbus Interrupts
VMEbus Interrupt Request Levels
Setting VMEbus Interrupt Vector Parameters
Specifying Module Switch Interrupt Vectors
Using VMEbus Software Byte Swapping
Sharing Memory Between Big/Little Endian Processors
VMEbus Slave Block Transfers
VMEbus Master Block Transfers with Local DMA
Interfaces for Master Block-Mode Transfers
Restriction on VMEbus Master Block Transfers
Realtime Interrupt-Handling Function rt_post_callout
RELATED INFORMATION

This document was created by man2html, using the manual pages.
Time: 02:40:19 GMT, October 02, 2010